Cp3 bt26 – National CP3BT26 User Manual

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CP3

BT26

20.7.7

Audio Receive Status and Control Register
(ARSCR)

The ARSCR register is used to control the operation of the
receiver path of the audio interface. It also holds bits which
report the current status of the receive FIFO. The CPU bus
master has read/write access to the ASCR register. At re-
set, this register is loaded with 0004h.

RXAF

The Receive Buffer Almost Full bit is set when
the number of data bytes/words in the receive
buffer is equal to the specified warning limit.
0 – Receive FIFO below warning limit.
1 – Receive FIFO is almost full.

RXF

The Receive Buffer Full bit is set when the re-
ceive buffer is full. The RXF bit is set when the
RWP is equal to the RRP and the last access
was a write to the FIFO.
0 – Receive FIFO is not full.
1 – Receive FIFO full.

RXE

The Receive Buffer Empty bit is set when the
the RRP is equal to the RWP and the last ac-
cess to the FIFO was a read operation (read
from ARDR).
0 – Receive FIFO is not empty.
1 – Receive FIFO is empty.

RXO

The Receive Overflow bit indicates that a re-
ceive shift register has overrun. This occurs,
when a completed data word has been shifted
into ARSR, while the receive FIFO was al-
ready full (the RXF bit was set). In this case,
the new data in ARSR will not be copied into
the FIFO and the RWP will not be increment-
ed. Also, no receive interrupt and DMA re-
quest will generated (even if enabled).
0 – No overflow has occurred.
1 – Overflow has occurred.

RXSA

The Receive Slot Assignment field specifies
which slots are recognized by the receiver of
the audio interface. Multiple slots may be en-
abled. If the frame consists of less than 4
slots, the RXSA bits for unused slots are ig-
nored. For example, if a frame only consists of
2 slots, RXSA bits 2 and 3 are ignored.

The following table shows the slot assignment
scheme.

After reset the RXSA field is clear, so software
must load the correct slot assignment.

RXDSA

The Receive DMA Slot Assignment field spec-
ifies which slots (audio channels) are support-
ed by DMA. If the RXDSA bit is set for an
assigned slot n (RXSAn = 1), the data re-
ceived within this slot will not be transferred
into the receive FIFO, but will instead be writ-
ten into the corresponding Receive DMA data
register (ARDRn). A DMA request n is assert-
ed, when the ARDRn is full and if the RMA bit
n is set. If the RXSD bit for a slot is clear, the
RXDSA bit is ignored. The following table
shows the DMA slot assignment scheme.

RXFWL

The Receive FIFO Warning Level field speci-
fies when a receive interrupt is asserted. A re-
ceive interrupt is asserted, when the number
of bytes/words in the receive FIFO is greater
than the warning level value. An RXFWL value
of 0 means that a receive interrupt is asserted
if one or more bytes/words are in the RX
FIFO. After reset, the RXFWL bit is clear.

RXSA

RXO

RXE

RXF RXAF

RXFWL

RXDSA

RXSA Bit

Slots Enabled

RXSA0

RXSA1

RXSA2

RXSA3

RXDSA Bit

Slots Enabled

for DMA

RXDSA0

RXDSA1

RXDSA2

RXDSA3