National CP3BT26 - Manual (Page 181)

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CP3
BT26
24.0 ACCESS.bus Interface
The ACCESS.bus interface module (ACB) is a two-wire se-
rial interface compatible with the ACCESS.bus physical lay-
er. It permits easy interfacing to a wide range of low-cost
memories and I/O devices, including: EEPROMs, SRAMs,
timers, A/D converters, D/A converters, clock chips, and pe-
ripheral drivers. It is compatible with Intel’s SMBus and Phil-
ips’ I
2
C bus. The ACB module can be configured as a bus
master or slave, and can maintain bidirectional communica-
tions with both multiple master and slave devices.
This section presents an overview of the bus protocol, and
its implementation by the ACB module.
„ ACCESS.bus master and slave
„ Supports polling and interrupt-controlled operation
„ Generate a wake-up signal on detection of a Start Con-
dition, while in power-down mode
„ Optional internal pull-up on SDA and SCL pins
24.1 ACB PROTOCOL OVERVIEW
The ACCESS.bus protocol uses a two-wire interface for bi-
directional communication between the devices connected
to the bus. The two interface signals are the Serial Data Line
(SDA) and the Serial Clock Line (SCL). These signals
should be connected to the positive supply, through pull-up
resistors, to keep the signals high when the bus is idle.
The ACCESS.bus protocol supports multiple master and
slave transmitters and receivers. Each bus device has a
unique address and can operate as a transmitter or a re-
ceiver (though some peripherals are only receivers).
During data transactions, the master device initiates the
transaction, generates the clock signal, and terminates the
transaction. For example, when the ACB initiates a data
transaction with an ACCESS.bus peripheral, the ACB be-
comes the master. When the peripheral responds and
transmits data to the ACB, their master/slave (data transac-
tion initiator and clock generator) relationship is unchanged,
even though their transmitter/receiver functions are re-
versed.
24.1.1 Data Transactions
One data bit is transferred during each clock period. Data is
sampled during the high phase of the serial clock (SCL).
Consequently, throughout the clock high phase, the data
must remain stable (see Figure 91). Any change on the SDA
signal during the high phase of the SCL clock and in the
middle of a transaction aborts the current transaction. New
data must be driven during the low phase of the SCL clock.
This protocol permits a single data line to transfer both com-
mand/control information and data using the synchronous
serial clock.
Figure 91. Bit Transfer
Each data transaction is composed of a Start Condition, a
number of byte transfers (programmed by software), and a
Stop Condition to terminate the transaction. Each byte is
transferred with the most significant bit first, and after each
byte, an Acknowledge signal must follow.
At each clock cycle, the slave can stall the master while it
handles the previous data, or prepares new data. This can
be performed for each bit transferred or on a byte boundary
by the slave holding SCL low to extend the clock-low period.
Typically, slaves extend the first clock cycle of a transfer if a
byte read has not yet been stored, or if the next byte to be
transmitted is not yet ready. Some microcontrollers with lim-
ited hardware support for ACCESS.bus extend the access
after each bit, to allow software time to handle this bit.
Start and Stop
The ACCESS.bus master generates Start and Stop Condi-
tions (control codes). After a Start Condition is generated,
the bus is considered busy and it retains this status until a
certain time after a Stop Condition is generated. A high-to-
low transition of the data line (SDA) while the clock (SCL) is
high indicates a Start Condition. A low-to-high transition of
the SDA line while the SCL is high indicates a Stop Condi-
tion (Figure 92).
Figure 92. Start and Stop Conditions
In addition to the first Start Condition, a repeated Start Con-
dition can be generated in the middle of a transaction. This
allows another device to be accessed, or a change in the di-
rection of the data transfer.
SDA
Data Line
Stable:
Data Valid Change
of Data
Allowed
SCL
DS075
Start
Condition Stop
Condition
SDA
S
SCL
P
DS076