National CP3BT26 - Manual (Page 33)

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CP3
BT26
8.3.3 Main Block Page Erase
A flash erase operation sets all of the bits in the erased re-
gion. Pages of a main block can be individually erased if
their write enable bits are set. This method cannot be used
to erase the boot area, if defined. Each page in Main Block
0 and 1 consists of 1024 bytes (512 words). Each page in
Main Block 2 consists of 512 bytes (256 words). To erase a
page, the following steps are performed:
1. Verify that the Flash Memory Busy (FMBUSY) bit in the
FMSTAT or FSMSTAT register is clear.
2. Prevent accesses to the flash memory while erasing is
in progress.
3. Set the Page Erase (PER) bit in the FMCTRL or FSM-
CTRL register.
4. Write to an address within the desired page.
5. Wait until the FMBUSY bit becomes clear again.
6. Check the Erase Error (EERR) bit in the FMSTAT or
FSMSTAT register to confirm successful erase of the
page.
7. Repeat steps 4 through 6 to erase additional pages.
8. Clear the PER bit.
8.3.4 Main Block Module Erase
A module erase operation can be used to erase an entire
main block. All sections within the block must be enabled for
writing. If a boot area is defined in the block, it cannot be
erased. The following steps are performed to erase a main
block:
1. Verify that the Flash Memory Busy (FMBUSY) bit in the
FMSTAT or FSMSTAT register is clear.
2. Prevent accesses to the flash memory while erasing is
in progress.
3. Set the Module Erase (MER) bit in the FMCTRL or
FSMCTRL register.
4. Write to any address within the desired main block.
5. Wait until the FMBUSY bit becomes clear again.
6. Check the Erase Error (EERR) bit in the FMSTAT or
FSMSTAT register to confirm successful erase of the
block.
7. Clear the MER bit.
8.3.5 Information Block Module Erase
Erasing an information block also erases the corresponding
main block. If a boot area is defined in the main block, nei-
ther block can be erased. Page erase is not supported for
information blocks. The following steps are performed to
erase an information block:
1. Verify that the Flash Memory Busy (FMBUSY) bit in the
FMSTAT or FSMSTAT register is clear.
2. Prevent accesses to the flash memory while erasing is
in progress.
3. Set the Module Erase (MER) bit in the FMCTRL or
FSMCTRL register.
4. Load the FMIBAR or FSMIBAR register with any ad-
dress within the block, then write any data to the FMIB-
DR or FSMIBDR register.
5. Wait until the FMBUSY bit becomes clear again.
6. Check the Erase Error (EERR) bit in the FMSTAT or
FSMSTAT register to confirm successful erase of the
block.
7. Clear the MER bit.
8.3.6 Main Block Write
Writing is only allowed when global write protection is dis-
abled. Writing by the CPU is only allowed when the write en-
able bit is set for the sector which contains the word to be
written. The CPU cannot write the Boot Area. Only word-
wide write access to word-aligned addresses is supported.
The following steps are performed to write a word:
1. Verify that the Flash Memory Busy (FMBUSY) bit in the
FMSTAT or FSMSTAT register is clear.
2. Prevent accesses to the flash memory while the write
is in progress.
3. Set the Program Enable (PE) bit in the FMCTRL or
FSMCTRL register.
4. Write a word to the desired word-aligned address. This
starts a new pipelined programming sequence. The
FMBUSY bit becomes set while the write operation is in
progress. The FMFULL bit in the FMSTAT or FSMSTAT
register becomes set if a previous write operation is still
in progress.
5. Wait until the FMFULL bit becomes clear.
6. Repeat steps 4 and 5 for additional words.
7. Wait until the FMBUSY bit becomes clear again.
8. Check the programming error (PERR) bit in the FM-
STAT or FSMSTAT register to confirm successful pro-
gramming.
9. Clear the Program Enable (PE) bit.
8.3.7 Information Block Write
Writing is only allowed when global write protection is dis-
abled. Writing by the CPU is only allowed when the write en-
able bit is set for the sector which contains the word to be
written. The CPU cannot write Information Block 0. Only
word-wide write access to word-aligned addresses is sup-
ported. The following steps are performed to write a word:
1. Verify that the Flash Memory Busy (FMBUSY) bit in the
FMSTAT or FSMSTAT register is clear.
2. Prevent accesses to the flash memory while the write
is in progress.
3. Set the Program Enable (PE) bit in the FMCTRL or
FSMCTRL register.
4. Write the desired target address into the FMIBAR or
FSMIBAR register.
5. Write the data word into the FMIBDR or FSMIBDR reg-
ister. This starts a new pipelined programming se-
quence. The FMBUSY bit becomes set while the write
operation is in progress. The FMFULL bit in the FM-
STAT or FSMSTAT register becomes set if a previous
write operation is still in progress.
6. Wait until the FMFULL bit becomes clear.
7. Repeat steps 4 through 6 for additional words.
8. Wait until the FMBUSY bit becomes clear again.
9. Check the programming error (PERR) bit in the FM-
STAT or FSMSTAT register to confirm successful pro-
gramming.
10. Clear the Program Enable (PE) bit.