Cp3bt26 – National CP3BT26 User Manual
Page 234
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234
CP3BT26
CAN
Memory
Registers
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CMBn.ID1
XI28
ID10
XI27
ID9
XI26
ID8
XI25
ID7
XI24
ID6
XI23
ID5
XI22
ID4
XI21
ID3
XI20
ID2
XI19
ID1
XI18
ID0
SRR
RTR
IDE
XI17 XI16 XI15
CMBn.ID0
XI14 XI13 XI12 XI11 XI10
XI9
XI8
XI7
XI6
XI5
XI4
XI3
XI2
XI1
XI0
RTR
CMBn.DATA0
Data
1.7
Data
1.6
Data
1.5
Data
1.4
Data
1.3
Data
1.2
Data
1.1
Data
1.0
Data
2.7
Data
2.6
Data
2.5
Data
2.4
Data
2.3
Data
2.2
Data
2.1
Data
2.0
CMBn.DATA1
Data
3.7
Data
3.6
Data
3.5
Data
3.4
Data
3.3
Data
3.2
Data
3.1
Data
3.0
Data
4.7
Data
4.6
Data
4.5
Data
4.4
Data
4.3
Data
4.2
Data
4.1
Data
4.0
CMBn.DATA2
Data
5.7
Data
5.6
Data
5.5
Data
5.4
Data
5.3
Data
5.2
Data
5.1
Data
5.0
Data
6.7
Data
6.6
Data
6.5
Data
6.4
Data
6.3
Data
6.2
Data
6.1
Data
6.0
CMBn.DATA3
Data
7.7
Data
7.6
Data
7.5
Data
7.4
Data
7.3
Data
7.2
Data
7.1
Data
7.0
Data
8.7
Data
8.6
Data
8.5
Data
8.4
Data
8.3
Data
8.2
Data
8.1
Data
8.0
CMBn.TSTP
TSTP
15
TSTP
14
TSTP
13
TSTP
12
TSTP
11
TSTP
10
TSTP
9
TSTP
8
TSTP
7
TSTP
6
TSTP
5
TSTP
4
TSTP
3
TSTP
2
TSTP
1
TSTP
0
CMBn.CNTSTAT DLC3 DLC2 DLC1 DLC0
Reserved
PRI3 PRI2 PRI1 PRI0 ST3
ST2
ST1
ST0
DMAC
Registers
20..16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADCA
Device A Address Counter
ADRA
Device A Address
ADCB
Device B Address Counter
ADRB
Device B Address
BLTC
N/A
Block Length Counter
BLTR
N/A
Block Length
DMACNTL
N/A
Res.
INCB
ADB
INCA
ADA
SW
RQ
Res.
OT
DIR
IND TCS
EO
VR
ETC
CH
EN
DMASTAT
N/A
Reserved
VLD
CH
AC
OVR
TC