Testbench, Receiver testbench description – Altera POS-PHY Level 4 IP Core User Manual

Page 99

December 2014

Altera Corporation

POS-PHY Level 4 IP Core User Guide

6. Testbench

The testbench stimulates the inputs and checks the outputs of the interfaces of the
POS-PHY Level 4 IP core, demonstrating basic functionality.

The remainder of this section contains the following information about the testbench:

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■

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Receiver Testbench Description

The testbench provided with the receiver variations of the POS-PHY Level 4 IP core
tests the following functions:

■

Using the Avalon-MM interface, program the calendar if Asymmetric Port
Support

is turned on (refer to

)

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Synchronization of the IP core with the SPI-4.2 training pattern

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Data integrity from the SPI-4.2 interface through the IP core variation to the
Atlantic back-end interface

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Ability to send data to multiple ports

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Verifies that the IP core correctly drives backpressure on the SPI-4.2 interface (this
test can be turned on and off)