Altera POS-PHY Level 4 IP Core - Manual (Page 11)

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
2. Getting Started
Design Flow
Figure 2–1 shows the stages for creating a system with the POS-PHY Level 4 IP core
and the Quartus ® II software. The sections in this chapter describe each stage.
IP Catalog and Parameter Editor
The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily
customize and integrate IP cores into your project. You can use the IP Catalog and
parameter editor to select, customize, and generate files representing your custom IP
variation.
The IP Catalog automatically displays the IP cores available for your target device.
Double-click any IP core name to launch the parameter editor and generate files
representing your IP variation. The parameter editor prompts you to specify your IP
variation name, optional ports, architecture features, and output file generation
options. The parameter editor generates a top-level .qsys or .qip file representing the
IP core in your project. Alternatively, you can define an IP variation without an open
Quartus II project. When no project is open, select the Device Family directly in IP
Catalog to filter IP cores by device.
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The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog
includes exclusive system interconnect, video and image processing, and other
system-level IP that are not available in the Quartus II IP Catalog.
Use the following features to help you quickly locate and select an IP core:
Figure 2–1. Design Flow
Specify Parameters
Compile Design
Program Device
Simulate with
Testbench
Apply Timing
Constraints