Altera POS-PHY Level 4 IP Core User Manual
Page 37
Chapter 3: Parameter Settings
3–17
Protocol Parameters
December 2014
Altera Corporation
POS-PHY Level 4 IP Core User Guide
1
FTL must be greater than zero.
This threshold is defined in terms of bytes, with a valid range from: N to buffer size,
in increments of N bytes, where:
■
N = 4 or 8 bytes for 32-bit data path variations
■
N = 8 or 16 bytes for 64-bit data path variations
■
N = 16 bytes for 128-bit data path variations
The N-byte values for the 32-bit and 64-bit variations depend on the Atlantic interface
width. If the Atlantic interface width is greater than the data path width, the larger
value for N is used.
For the DIP-4 good and DIP-4 bad threshold values, two 4-bit inputs are associated
with the DIP-4 OOS state machine: good_level (ctl_rd_dip4_good_threshold) and
bad_level
(ctl_rd_dip4_bad_threshold).
If the stat_rd_dip4_oos signal is high, and all of the DIP-4s in the control words
received in the current clock cycle (up to 8 in 128-bit mode) are good, the good counter
is incremented by 1; otherwise it is reset to 0. If the good counter reaches the
good_level
threshold, the stat_rd_dip4_oos flag is cleared. A good_level of 0 is
invalid.
If the stat_rd_dip4_oos signal is low, and all of the DIP-4s in the control words
received in the current clock cycle (up to 8 in 128-bit mode) are errored, the bad
counter is incremented by 1; otherwise it is reset to 0. If the bad counter reaches the
bad_level
threshold, the stat_rd_dip4_oos flag is asserted. A bad_level of 0 is
invalid.
1
The receiver may need to receive more control word DIP-4 errors than the DIP-4 bad
threshold
parameter set in the wizard, for stat_rd_dip4_oos to go high.
f
For more information, refer to