Altera POS-PHY Level 4 IP Core - Manual (Page 100)

6–2 Chapter 6: Testbench
Receiver Testbench Description
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
The testbench consists of three basic modules: packet generation, user receiver
variation, and a data analyzer. All testbench modules are in the <variation name>_tb.v
file. The testbench also consists of multiple support modules for pin monitoring, clock
generation, and reset generation (refer to
Figure 6–1 ). The packet generation module
generates SPI-4.2 packets. These packets are received by the receiver IP core, which
processes the packets and converts them to Atlantic interface format. Finally, the data
analyzer module receives the data from the Atlantic interface and verifies the
correctness of the data with an individual monitor for each port.
The packet generation module begins by sending the idle pattern (16'h000f) and then
the training pattern (16'h0fff,16'hf000) until the POS-PHY Level 4 receiver IP core is
synchronized to the data source.
The packet generation module then begins sending packets of lengths defined by the
top-level testbench. To allow for automated packet checking, a special packet format
is used.
Table 6–1 shows the format of each packet.
Figure 6–1. Receiver Testbench
Packet Generation
POS-PHY Level 4
Atlantic Interface
Data Analyser
(one per port)
Clock
Generator
Pin Monitor Reset
SPI-4.2
Interface Device Under Test
Atlantic
Interface
POS-PHY
Variation
Level 4
Receiver
Table 6–1. Packet Format
Packet Byte Format Description
Header byte {0,0,len[5:1],ext}
Contains information about the packet. len represents the length of
the packet if the length can be encoded in six bits. If the length is
beyond 32 bits, ext is set to indicate that the next byte in the packet
contains the length information.
Extra length byte {size[16:0]}
If ext is 1, the extended expected packet size shows the length of the
packet including the header (size > 16 bytes) (optional).
Number byte {N[7:0] ^ port_num}
Packet number (packet number begins at 'h01 and is incremented by
one for each packet) XORed with the port number.
Payload bytes {N++^ port_num}
The following bytes in the packet are incremented by one and XORed
with the port number.