Altera POS-PHY Level 4 IP Core - Manual (Page 106)

6–8 Chapter 6: Testbench
Transmitter Testbench Description
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
When an error is asserted on the Atlantic interface with a valid EOP, and an end of
packet abort message is sent to the SPI-4.2 interface, it is not counted as an error in the
data and does not cause the testbench to fail.
The packet tasks for each port are called in parallel via a fork or join statement.
Arbitration is handled in the data generator module and varies for each buffer mode.
■ For individual buffers variations, the packets can be written in parallel.
■ For shared buffer with embedded addressing variations, the arbiter selects each
port in a round-robin fashion, switching to the next port at a fixed interval.
The packets have lengths defined in the top-level testbench and follow the format in
Table 6–6 .
The testbench concludes by checking that all of the packets have been received. In
addition, it checks that the POS-PHY Level 4 packet receiver (packet analyzer
module) has not detected any errors in the received packets. If no error has been
detected, and all packets have been received, the testbench issues a message stating
that the simulation was successful.
If an error has been detected, a message states that the testbench has failed. If not all
packets have been detected, a message states that the testbench is incomplete. The
tb.exp_chk_cnt
variable determines the number of checks done to ensure
completeness of the testbench. For each port tested, one completeness check is done.
In addition, a preliminary check is done to make sure synchronization is complete,
and a final check is done for the conclusion of the testbench.
Optionally, the testbench can test backpressure on the SPI-4.2 interface. When the
backpressure
variable is defined, backpressure is generated on one or more ports, by
first setting the status for the appropriate ports to satisfied. This action informs the
POS-PHY Level 4 transmitter IP core to not send data to those ports (specific reaction
to backpressure depends on the variation selected). The data generator continues to
write to the buffers until the Atlantic aN_arxdav or aN_atxdav signal goes high,
indicating that the buffer is nearly full. The testbench then turns the status for the
satisfied ports back to starving or hungry. The POS-PHY Level 4 transmitter IP core
then resumes sending packets to those ports. When the FIFO buffer is satisfied, the
status on the SPI-4.2 interface notifies the data generator module to stop sending data.
There is a break in packet generation during which idles are sent. After the status
returns to the hungry state, the packet generation resumes.
Table 6–6. Packet Format
Packet Byte Format Description
Header byte {0,0,len[5:1],ext}
Contains info about the packet. len is the length of the packet if the
length can be encoded in six bits. If the length is beyond 32 bits, ext is
set to indicate that the next byte in the packet contains the length
information.
Extra length byte {size[16:0]}
If ext is 1, the extended expected packet size shows the length of the
packet including the header (size > 16 bytes) (optional).
Number byte {N[7:0] ^ port_num}
Packet number (packet number begins at 'h01 and is incremented by
one for each packet) XORed with the port number.
Payload bytes {N++^ port_num}
The following bytes in the packet are incremented by one and XORed with
the port number.