Altera POS-PHY Level 4 IP Core - Manual (Page 69)

Chapter 4: Functional Description—Receiver 4–31
Latency Information
December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
Table 4–13 lists the latency numbers for receiver IP cores.
1 Data latency:
■ The values in Table 4–13 do not include the latency through the user-side buffers.
■ For 64- and 128-bit data path width variations, the values assume that the clock-
crossing buffer is empty. Additional latency should be added if multiple continue
traffic is expected.
■ The DPA adds 32 bytes for a 128-bit data path, and 16 bytes for a 64-bit data path.
For 64-bit variations using Stratix GX devices, the DPA adds an additional 24 bytes
due to the extra clocking stage with the PLL.
■ The external support in the shared buffer with embedded addressing mode adds
8, 4, or 2 bytes for 128-, 64-, and 32-bit data path widths, respectively.
1 For status latency, the values do not include waiting for the appropriate time slot in
the status channel for the status to be transmitted.
Table 4–13. Receiver Latency
IP core
Data Latency
(Bytes on SPI-4.2 Interface)
Status Transmit Latency
(Bytes on SPI-4.2 Interface)
128-bit shared buffer with embedded addressing 272 320
128-bit individual buffers 288 320
64-bit shared buffer with embedded addressing 152 320
64-bit individual buffers 160 320
32-bit shared buffer with embedded addressing 36 320
32-bit individual buffers 72 320