Altera POS-PHY Level 4 IP Core User Manual
Page 65
Chapter 4: Functional Description—Receiver
4–27
Signals
December 2014
Altera Corporation
POS-PHY Level 4 IP Core User Guide
rav_clk
Input
rav_clk
Avalon-MM clock. Signals prefixed with rav_ are
synchronous to this clock. This port is absent if
asymmetric port support is turned off.
rav_address[3:0]
Input
Avalon-MM address. This port is absent if asymmetric
port support is turned off.
rav_chipselect
Input
Avalon-MM chip select. This port is absent if
asymmetric port support is turned off.
rav_write
Input
Avalon-MM write enable. This port is absent if
asymmetric port support is turned off.
rav_read
Input
Avalon-MM read enable. This port is absent if
asymmetric port support is turned off.
rav_writedata[15:0]
Input
Avalon-MM write data. This port is absent if asymmetric
port support is turned off.
rav_readdata[15:0]
Output
Avalon-MM write data. This port is absent if asymmetric
port support is turned off.
rav_waitrequest
Output
Avalon-MM wait request. This port is absent if
asymmetric port support is turned off.
Note to
:
(1) The nominal phase offset between the clock and data is 180
, you may want to put some timing constraints between the clock and status block.
You must take into account the trace delay difference between the clock and status block, to compensate for any difference.
Table 4–9. SPI-4.2 Channel Control and Status (Part 3 of 3)
Signal
Direction
Clock Domain
Description
Table 4–10. DPA Control and Status
Signal
Direction
Clock Domain
Description
err_rd_dpa
Output
rdint_clk
Error flag to indicate that the DPA circuitry
could not find byte alignment. This port is
absent if DPA is turned off.
stat_rd_dpa_locked
Output
When this signal is high, it indicates that
the DPA aligner has aligned to the training
pattern. This port is absent if DPA is turned
off.
stat_rd_dpa_lvds_locked[16:0]
Output
When this signal is high, it indicates that
the DPA PLL has locked. This port is absent
if DPA is turned off.
ctl_rd_dpa_force_unlock
Input
Forces the DPA circuitry and PLL to unlock
and retrain. This port is absent if DPA is
turned off.