Altera POS-PHY Level 4 IP Core - Manual (Page 3)

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
1. About This IP Core
The Altera ® POS-PHY Level 4 MegaCore ® function is an IP core that performs high-
speed cell and packet transfers between physical and link-layer devices.
Release Information
Table 1–1 provides information about this release of the Altera ® POS-PHY Level 4 IP
core.
f For more information about this release, refer to the MegaCore IP Library Release Notes
and Errata .
Altera verifies that the current version of the Quartus ® II software compiles the
previous version of each IP core. The MegaCore IP Library Release Notes and Errata
report any exceptions to this verification. Altera does not verify compilation with IP
core versions older than one release.
Device Family Support
IP cores can provide the types of support for target Altera device families described in
Table 1–2 .
Table 1–1. POS-PHY Level 4 IP Core Release Information
Item Description
Version 14.1
Release Date December 2014
Ordering Code IP-POSPHY4
Product ID 0088
Vendor ID 6AF7
Table 1–2. Altera IP Core Device Support Levels
FPGA Device Families
Preliminary—The core is verified with preliminary timing models for this device family. The core
meets all functional requirements, but might still be undergoing timing analysis for the device
family. It can be used in production designs with caution.
Final—The core is verified with final timing models for this device family. The core meets all
functional and timing requirements for the device family and can be used in production designs.