Altera POS-PHY Level 4 IP Core - Manual (Page 28)

3–8 Chapter 3: Parameter Settings
Optional Features
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
If you turn on Ignore backpressure (only available when you turn on Shared buffer
with embedded addressing
), the IP core ignores the backpressure from the receiver
and simply sends data whenever the buffer is not empty. The IP core stops reading
from the buffer only when the status framer is out of synchronization, when a training
pattern is inserted, or when there is not enough data to complete a burst. The user
logic is responsible for using the status outputs from the IP core to schedule data
writes into the buffer appropriately.
If you turn off Ignore backpressure, a simple scheduling algorithm is employed. If
the status received for any port is satisfied, the transmitter stops reading from the
buffer on the next EOP or burst unit size boundary. If all ports are hungry or starving,
the transmitter sends the data in the buffer. So a satisfied status received for one port
prevents transmission for any port, leading to head-of-line blocking.
If you turn on Switch on end-of-packet, the scheduler stops sending from the current
port, and switches ports at the end of burst (that is, when the credits have all been
consumed), as well as when an EOP is sent. If you turn off Switch on end-of-packet,
the scheduler switches ports at the end of the burst (also includes switching when the
buffer is empty).
1 This option applies only to the individual buffers mode, and allows you to
parameterize the port switching capabilities of the transmit scheduler.
f For more information, refer to “Individual Buffers Transmit Scheduler (tx_sched)” on
page 5–3 .
Turn on Burst Limit Enable, if you want the transmitter to limit the maximum size of
bursts it sends. Set the maximum burst value with the Burst Limit option (on the
Protocol Parameters
tab). At the end of a burst limit a control word is inserted.
Receiver Options
If you turn off Ignore LVDS DPA locked after training, which is only available for
Stratix II devices, a loss of dpa_lvds_locked causes the IP core to stop processing data,
sends framing, and there is data loss and the possibility of MSOP/EOP errors. If you
turn on Ignore LVDS DPA locked after training, a loss of dpa_lvds_locked does not
trigger stop and framing, and data continues to process normally. You must monitor
the DIP4 error signal to assess if the data is correct or not and trigger a retrain or not.
1 For Stratix III and Stratix IV devices, the dpa_lvds_locked signal never goes low, so
the IP core behaves as if you turned on Ignore LVDS DPA locked after training.
If the signal stat_rd_lvds_lock goes low during operation (after training), the IP core
assumes that the lock is lost due to external conditions such as jitter. This signal goes
low if the capture phase of the hardware DPA block changes by two or more phases.
The two phases correspond to a amount that is lower than the accepted threshold for
the SPI4.2 Specification. When the signal goes low, the IP core states it is out of
synchronization and requests a new training sequence.
In some cases, it is better to ignore this signal and rely on the error checking
mechanisms or SPI4.2, by checking the DIP4 calculation. You then have to externally
request the retraining and unlock the DPA block.