Spare pins, Jtag scan chain – Altera POS-PHY Level 4 IP Core User Manual
Page 119
Appendix D: Board Design
D–3
Design for Testability
December 2014
Altera Corporation
POS-PHY Level 4 IP Core User Guide
SPI-4.2 Status Interface
■
tstat[1:0]
■
tsclk
Other Useful Debug Signals
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FPGA reset
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stat_ts_sync
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err_ts_dip2
■
err_ts_frm
■
trefclk
1
In addition to these transmitter signals, it may be useful to provide test points for
similar debug and status signals from the adjacent device.
Spare Pins
The SignalProbe feature in the Quartus II software allows you to route signals inside
the device to output pins so you can view the signals on an oscilloscope or logic
analyzer, without recompiling the design.
Altera recommends that you have a set of unused FPGA pins connected to test points
or connectors for an oscilloscope or logic analyzer. If you find problems in the design,
you can easily route internal signals to these connectors or test points to accelerate
debugging.
The following are SignalProbe feature requirements:
■
Pins for analysis must not already be assigned for use in the design, cannot be a
group or bus, and cannot have a carry or cascade fan out.
■
Nodes for analysis must be post-compilation, and cannot be carry-out or cascade-
out signals or groups.
f
For more information on using the SignalProbe feature, refer to “Performing a
SignalProbe Compilation on a Design” in Quartus II Help.
JTAG Scan Chain
Altera recommends that you make the JTAG scan chain available for the Altera
SignalTap II logic analyzer. The SignalTap II application implements a small logic
analyzer inside the FPGA, and uses memory blocks to store waveforms. The
waveforms are sent via the JTAG interface to the SignalTap waveform viewer
application, allowing you to see what is happening inside the device.
f
For further information, refer to