Altera POS-PHY Level 4 IP Core - Manual (Page 24)

3–4 Chapter 3: Parameter Settings
Basic Parameters
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
For transmitters for individual buffers variations, a credit-based scheduler is
provided. This scheduler decodes the incoming status channel and decides from
which FIFO buffer (port) to transmit.
The individual buffers for transmitters offer the following advantages:
■ A simple user interface
■ Full scheduler
■ No head-of-line blocking
■ Per-port backpressure
f
For further information on individual buffers for transmitters, refer to “Individual
Buffers” on page 5–3 .
For receivers, the individual buffers offer the following advantages:
■ A simple user interface
■ No head-of-line blocking
■ The POS-PHY Level 4 IP core handles all of the backpressure automatically
f
For further information on individual buffers for receivers, refer to “Individual
Buffers” on page 4–6 .
The SPI-4.2 protocol supports from 1 to 256 ports. When you select the number of
ports, you determine the mode of operation. Single-PHY operation for one port; or
multi-PHY for two to 256 ports. For example, when interfacing to a 10-channel Gbit
Ethernet MAC device the number of ports is 10.
When you use the shared buffer with embedded addressing, the Number of ports
determines the number of port addresses supported by the POS-PHY Level 4 protocol
portion of the IP core, such as the status generator and error checker. Port addresses 0
to 255 can always be sent and received when using Shared buffer with embedded
addressing
.
For the shared buffer with embedded addressing, the Buffer size defines the size of
the shared embedded address buffer. For the individual buffers, the Buffer size
defines the size of each buffer. The POS-PHY Level 4 IP core supports the following
sizes (per buffer):
■ 512 bytes
■ 1,024 bytes
■ 2,048 bytes
■ 4,096 bytes
■ 8,192 bytes
■ 16,384 bytes
■ 32,768 bytes