Altera POS-PHY Level 4 IP Core - Manual (Page 39)

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
4. Functional Description—Receiver
The POS-PHY Level 4 IP core consists of the main SPI-4.2 processing logic, and
configurable Atlantic
™ first-in first-out (FIFO) buffers. When the POS-PHY Level 4 IP
core is configured as a receiver, data flows from the SPI-4 interface to the Atlantic
interface.
Features
■ Accepts packets from a SPI-4.2 transmitter
■ Processes control words
■ Detects diagonal interleaved parity (DIP-4) errors
■ Detects SPI-4.2 protocol errors
■ Performs start-of-packet (SOP) alignment and Atlantic conversion
■ Buffers packets on a per-port or per-interface basis
■ Detects buffer fill levels and generates the status channel
Block Description
Figure 4–1 on page 4–1 shows the blocks and clocks that comprise the receiver IP core.
Figure 4–1. Block Diagram—Receiver (Note 1)
Note to Figure 4–1 :
(1) The dotted lines illustrate the clock domain separations.
Data Receiver
And
Serial-to-Parallel
Converter
DPA Channel
Aligner
Status PHY Status FSM
Status
Register
Status Hold
Status
Calculator
Data
Processor Atlantic
Buffer 0
Atlantic
Interface 0
SPI4.2
Interface
rdclk
rxsys_clk
rdint_clk
rav_clk
rsclk
Atlantic
Buffer N
Atlantic
Interface N