Altera POS-PHY Level 4 IP Core - Manual (Page 121)

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
E. Programming the SPI-4.2 Calendar via
the Avalon Memory-Mapped Interface
Introduction
An Avalon ® Memory-Mapped (Avalon-MM) interface is included with some POS-
PHY Level 4 IP core variations for easy configurability of some parameters, provided
the required features have been turned on in IP Toolbench.
Specifically, if the Asymmetrical Port Support is turned on, the Avalon-MM interface
allows you to program the SPI-4.2 calendar. It also allows you to control the associated
Hitless B/W reprovisioning
feature, provided that option is turned on. You can
thereby allocate more bandwidth to a certain port by repeating it any number of times
in the calendar sequence.
The Asymmetrical Port Support allows the SPI-4.2 status channel to have a calendar
length of up to 1,024 slots, where each slot can be associated with any valid port-
address number. The range of valid port numbers is zero to the number of ports - 1.
You can set the maximum calendar length and number of ports for your variation of
the POS-PHY Level 4 IP core using IP Toolbench within the Quartus II software (refer
to
Chapter 2, Getting Started for detailed instructions).
This approach requires that the receiver and transmitter IP cores maintain identical
tables that map each calendar slot number to a port address number. When the hitless
bandwidth reprovisioning feature is turned on, two calendars are supported thereby
requiring two tables. Internally, the POS-PHY Level 4 IP core stores the mappings in a
memory which must be configured after reset. Access to the table memory is provided
via the Avalon-MM register fields: CALMEM_ADR, CALMEM_DAT0, and CALMEM_DAT1.
f For details, refer to the “Avalon-MM Interface Register Map” on page 4–28 , and
“Avalon-MM Interface Register Map” on page 5–24 .
Programming the SPI-4.2 Calendar
This section provides a step-by-step example, using a 4-port receiver variation with
hitless bandwidth reprovisioning, and the following calendar length and port address
number values:
■ Calendar 0 (CAL0) has 5 slots, and port 3 is allocated two calendar slots. The
desired calendar sequence may be: 0,3,2,3,1.
■ Calendar 1 (CAL1) has 3 slots, and only 3 ports are enabled. The desired calendar
sequence may be: 1,2,3.
To program the calendar, follow these steps:
1
These instructions assume that you are familiar with the Avalon-MM interface and the
Avalon Interface Specifications , and that you have read the previous chapters of this user
guide.
1. Disable the status channel by writing a 1 to the RSFRM bit.