Altera POS-PHY Level 4 IP Core - Manual (Page 40)

4–2 Chapter 4: Functional Description—Receiver
Block Description
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
This section describes the top-level blocks of the POS-PHY Level 4 receiver IP core.
Data Receiver and Serial-to-Parallel Converter (rx_data_phy_altlvds)
Data and control words arrive on the rdat bus, and are sampled on both edges of
rdclk
. Payload and control words contain two bytes, where bit 15 is the most
significant bit (MSB) and bit 8 is the least significant bit (LSB) of the first byte, and bit
7 is the MSB and bit 0 is the LSB of the second byte.
For 128- and 64-bit variations, an ALTLVDS_RX IP core deserializes the SPI-4.2
rdat
/rctl lines into words at or the rdat data rate, respectively. The rdint_clk
is derived from the rdclk input pin, and is the clock that drives the internal logic
elements for the receiver.
For 32-bit (quarter-rate) variations, an ALTDDIO_IN IP core deserializes the SPI-4.2
rdat
/rctl lines into words at  the rdat data rate.
For rates above 311 Mbps, the Stratix ® III, Stratix II, Stratix GX, and Stratix devices
include a dedicated SERDES (ALTLVDS IP core) implemented in LVDS I/Os. For
rates below 250 Mbps, LVDS I/O pins are used.
1
A fast phase-locked loop (PLL) is required for the ALTLVDS SERDES.
f
For more information on the ALTLVDS_RX and ALTDDIO_IN IP cores, refer to
Quartus
® II Help, to the SERDES Transmitter/Receiver ALTLVDS IP Core User Guide , or
to the ALTDDIO IP Core User Guide .
DPA Channel Aligner (rx_data_phy_dpa)
In the Stratix III, Stratix II, and Stratix GX device families, the ALTLVDS_RX IP cores
support an optional DPA feature that can compensate for trace length mismatches and
variations due to process, voltage, and temperature (PVT).
The DPA feature includes the following functions:
■ Supports data rates from 415 Mbps to 1 Gbps in Stratix GX devices
■ Supports data rates from 415 Mbps to 1,250 Gbps in Stratix III devices and to 1,050
Gbps in Stratix II devices
■ At reset, it performs channel alignment using SPI-4.2 training patterns
compensating for static clock-channel and channel-to-channel skew
■ After reset, it dynamically follows changing clock-channel and channel-to-channel
skew without using SPI-4.2 training patterns
■ Supports a total skew of 4.5 bits, with 0.5 bits of the total allowed after reset in
Stratix GX devices
■ Supports a total skew of 4.4 bits, with 0.4 bits of the total allowed after reset in
Stratix III and Stratix II devices