Altera POS-PHY Level 4 IP Core - Manual (Page 131)

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
G. Conversion from v2.2.x
Introduction
The POS-PHY Level 4 IP core version 2.4.x and 2.3.x are not drop-in replaceable
functions for earlier versions. The clocking structure of version 2.4.x and 2.3.x have
been modified to allow the Atlantic
™ first-in first-out (FIFO) buffers to use either a
single clock domain, or multiple clock domains. As a result, the clock signal names
and the signals naming conventions have changed. Some of the control and status
signals are now synchronous to a different clock domain.
1
The restrictions outlined in Table C–1 on page C–1 must be followed for the clocking
structure to operate properly.
The POS-PHY Level 4 IP core version 2.4.x and 2.3.x also provide support for
asymmetric ports and hitless bandwidth reprovisioning. When Asymmetric ports
support
is turned on, an Avalon ® Memory-Mapped (Avalon-MM) interface is
instantiated in the IP core. The signals associated with the Avalon-MM interface were
not available in previous versions of the IP core.
Receiver Signals
In the 2.2.x versions of the IP core, the logic was located in the reference clock
(rrefclk) domain. Writing to the Atlantic FIFO buffer also occurred in the rrefclk
domain. The rrefclk was derived from rdclk (SPI-4.2 receive clock). Signals
synchronous to rrefclk were infixed by _rr_. Reading from the Atlantic FIFO buffer
was done using the Atlantic clock (aN_arxclk).
In the 2.4.x and 2.3.x versions of the IP core, rrefclk has been renamed rdint_clk.
Signals synchronous to rdint_clk are infixed by _rd_. Only part of the function is
synchronous to rdint_clk; the bulk of the function is synchronous to rxsys_clk. The
rxsys_clk
clock is an input to the IP core, and signals synchronous to this clock are
infixed by _ry_. In 32-bit data path, and shared buffer with embedded addressing
variations, the rxsys_clk is not input and is internally assigned rdint_clk. The
signals remain infixed by _ry_, and the clock domain is still referred to as rxsys_clk.
In the single clock domain mode, rxsys_clk writes to the Atlantic FIFO buffer. In the
multiple clock domain mode, reading from the Atlantic FIFO buffer is done using the
Atlantic clock (aN_arxclk). For more information, refer to the
“Clock Structure”
section of the “Functional Description—Receiver” chapter.