Altera POS-PHY Level 4 IP Core - Manual (Page 118)

D–2 Appendix D: Board Design
Design for Testability
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
Probe Points
Altera recommends that you make some of the POS-PHY Level 4 IP core pins and
status signals available for probing using test points or connectors for logic analyzers.
Good debug connectors take little space on a PCB and have a minimal effect on signal
integrity (for example, Samtec ASP65067-01 connectors).
Receiver IP Cores
The following signals connected to the POS-PHY Level 4 receiver IP cores should be
made available for debugging:
■ SPI-4.2 data interface signals:
■ rdat[15:0]
■ rctl
■ rdclk
■ SPI-4.2 status interface signals:
■ rstat[1:0]
■ rsclk
■ Other useful debug signals:
■ FPGA reset
■ stat_rd_dpa_locked
■ stat_rd_dpa_lvds_locked
■ err_rd_dip4
■ err_ry_msopN
■ err_ry_meopN
■ rdint_clk
■ aN_arxerr
■ aN_arxeop
■ aN_arxclk
1
In addition to these receiver signals, it may be useful to provide test points for similar
debug and status signals from the adjacent device.
Transmitter IP Cores
The following signals connected to the POS-PHY Level 4 transmitter IP cores should
be made available for debugging:
SPI-4.2 Data Interface
■ tdat[15:0]
■ tctl
■ tdclk