Zilog Z08470 - Manual (Page 92)

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UM008101-0601 Direct Memory Access
Figure 30. Write Register Organization (left) and Read Register Organization (right)
WRQ
WR1
WR2
WR3
WR4
WR6
WR5
Data
BUS 7 0
Base Register Byte
Base Register Byte
Base Register Byte
Base Register Byte
Base Register Byte
Base Register Byte
Base Register Byte
Port A Starting Address Register
15 8 7 0
Block Length Register
Port A Variable Timing
Port B Variable Timing
Mask Byte
Match Byte
15 8 7 0
Port B Starting Address Register
Interrupt Control Byte
Pulse Control Byte
Interrupt Vector
Read Mask
Data
BUS
0
Port A Address Counter
Byte Counter
RR4 RR3
RR2 RR1
Port B Address Counter
RR6 RR5
Status Byte
RR0
Port A Address Counter (see right illustration)
Port B Address Counter (see right illustration)
Byte Counter (see right illustration)
Status Byte (see right)