Zilog Z08470 - Manual (Page 272)

< %27 2GTKRJGTCNU
7UGT /CPWCN
UM008101-0601 Serial Input/Output
252
CRC character has been loaded to the receive buffer, or 20 times (the
previous 16 plus 3-bit buffer delay and 1-bit input delay) after the last bit
is at the RxD input, before CRC calculation is complete. A faster external
clock can be gated to the Receive Clock input to supply the required 16
cycles. The Transmit and Receive Data Path diagram (Figure 109) illus-
trates the various points of delay in the CRC path.
The typical program steps that implement a half-duplex Bisync Receive
mode are illustrated in Table 7. The complete set of command and status
bit definitions are explained under
“Programming” on page 272 .
Table 7. Bisync Receive Mode
Function Typical Program Steps Comments
Register Information Loaded
Initialize WR0 Channel Reset, Reset Receive CRC
Checker Reset SIO; initialize receive CRC
checker
WR0 Pointer 2
WR2 Interrupt Vector Channel B only
WR0 Pointer 4
WR4 Parity Information, Sync Modes
Information, Clock Mode Issue Receive Parameters
WR0 Pointer 5, Reset External Status
Interrupt
WR5 Bisync CRC-16, Data Terminal Ready
WR0 Pointer 3
WR3 Sync Character Load Inhibit, Receive
CRC Enable; Enter Hunt Mode, Auto
Enables, Receive Character Length Sync Character Load Inhibit strips all
the leading sync characters at the
beginning of the message. Auto Enables
enables the receiver to accept data only
after the DCD input is active.
WR0 Pointer 6
WR6 Sync Character 1
WR0 Pointer 7
WR7 Sync Character 2