Zilog Z08470 - Manual (Page 280)

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7UGT /CPWCN
UM008101-0601 Serial Input/Output
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has been completely sent, the Transmit Buffer Empty status bit is set and an
interrupt is generated to indicate to the CPU that another message can
begin. This interrupt occurs because CRC is sent and the flag is loaded. If
no more messages are to be sent, the program can terminate transmission
by resetting RTS, disabling the transmitter.
In the SDLC mode, reset the Transmit Underrun/EOM status bit immedi-
ately after the first character is sent to the Z80 SIO. When the Transmit
Underrun is detected, this ensures that the transmission time is filled by
CRC characters, giving the CPU enough time to issue the Send Abort
command. This procedure also stops the flags from going on the line
prematurely and eliminates the possibility of the receiver accepting the
frame as valid data. For example, the data pattern, immediately preceding
the automatic flag insertion, could match the CRC checker, thereby giving a
false CRC check result. The External/Status interrupt is generated when-
ever the Transmit Underrun/EOM bit is set as a result of the Transmit
Underrun condition.
The transmit underrun logic provides additional protection from premature
flag insertion if the proper response is given to the Z80 SIO by the CPU
interrupt service routine. The following example illustrates this point:
1. The Z80 SIO interrupts with the Transmit Buffer Empty status bit set.
2. The CPU does not respond in a timely manner, which causes a
Transmit Underrun condition.
3. The Z80 SIO starts sending CRC characters (two bytes).
4. The CPU eventually satisfies the Transmit Buffer Empty interrupt
with a data character that follows the CRC character being
transmitted.
5. The Z80 SIO sets the External/Status interrupt with the Transmit
Underrun/EOM status bit set
6. The CPU recognizes the Transmit Underrun/EOM status and
determines from its internal program status that the interrupt is not
“end of message”.