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7UGT /CPWCN
UM008101-0601
Parallel Input/Output
Figure 11.
Interrupt Acknowledge Timing
Figure 12.
Return from Interrupt Cycle
Φ
M1
IORQ
INT
IORQ and M1
indicate Interrupt
IEO
IEI
Last T
State
T
1
T
2
T
W
*
T
3
T
W
*
Sample
INT
Acknowledge (INTA)
IEO
CLK
IEI
RD
M1
T
1
T
2
T
3
T
4
D
7
–D
0
T
1
T
2
T
3
T
4
T
1
ED
4D
