Zilog Z08470 - Manual (Page 208)

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UM008101-0601 Parallel Input/Output
In addition to the automatic power-on reset, the PIO can be reset by
applying an M1 signal without the presence of a RD or IORQ signal. If no
RD or IORQ is detected during M1, the PIO enters the reset state immedi-
ately after the M1 signal goes inactive. This reset allows a single external
gate to generate a reset without a power-down sequence. The 40-pin pack-
aging requires this routine.
When the PIO enters the internal reset state, it is held there until the PIO
receives a control word from the CPU.
Loading The Interrupt Vector
The PIO is designed to operate with the Z80 CPU using the Mode 2 inter-
rupt response. This mode requires that an interrupt vector be supplied by
the interrupting device. This vector is used by the CPU to form the address
for the interrupt service routine of that port. This vector is placed on the
Z80 data bus during an interrupt acknowledge cycle by the highest priority
device requesting service at that time. (Refer to the Z80 CPU User’s
Manual Section for details on how an interrupt is serviced by the CPU).
The interrupt vector is loaded to the PIO by writing a control word to the
appropriate PIO port using the following format:
D0 functions as a flag bit, which when Low, loads V7 through V1 to the
vector register. At interrupt acknowledge, the vector of the interrupting port
appears on the Z80 data bus exactly as illustrated in the diagram above.
Signifies this Control Word
is an Interrupt Vector
V7 V6 V5 V4
D7 D6 D5 D4 D3 D0 D2 D1
V3 V2 V1 0