Zilog Z08470 - Manual (Page 320)

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7UGT /CPWCN
UM008101-0601 Serial Input/Output
300
CRC/Framing Error (D6)
If a Framing Error occurs (asynchronous modes), this bit is set (and not
latched) for the receive character in which the Framing Error occurred.
Detection of a Framing Error adds an additional one-half bit time to the
character time, so the Framing Error is not interpreted as a new start bit. In
synchronous and SDLC modes, this bit indicates the result of comparing
the CRC checker to the appropriate check value. This bit is reset by issuing
an Error Reset command. The bit is not latched, so it is always updated
when the next character is received. When used for CRC error and status in
synchronous modes, it is usually set because most bit combinations result
in a non-zero CRC except for a correctly completed message.
End-of-Frame (D7)
This bit is used only with the SDLC mode and indicates that a valid ending
flag has been received and that the CRC Error and Residue codes are also
valid. This bit can be reset by issuing the Error Reset command. It is also
updated by the first character of the following frame.
Read Register (Channel B Only)
This register contains the interrupt vector written into WR2 if the Status
Affects Vector control bit is not set. If the control bit is set, it contains the
modified vector listed in the Status Affects Vector paragraph of the Write
Register 1 section. When this register is read, the vector returned is modi-
fied by the highest priority interrupting condition at the time of the read. If
no interrupts are pending, the vector is modified with V3 = 0, V2 = 1, and
V1 = 1. This register is read only through Channel B.
Table 35. Interrupt Vector
D7 D6 D5 D4 D3 D2 D1 D0
V7 V6 V5 V4 V3* V2* V1* V0
*Variable if ‘Status Affects Vector’ is programmed