Zilog Z08470 User Manual
Page 134
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UM008101-0601
Direct Memory Access
Bit 0
Indicates whether the DMA has requested the bus after the fast
LOAD command. 1 indicates yes, 0 indicates no.
Bit 1
Indicates whether the DMA’s RDY pin currently has a signal input
that is defined as active by bit 3 of WR5. 1 indicates an active Ready line. 0
indicates an inactive Ready line.
Bit 2
Undefined.
Bit 3
Indicates the state of the Interrupt Pending (IP) latch. A 0 indicates
that an interrupt is pending (the DMA has its INT line active if the interrupt
has not been acknowledged). A 1 indicates no interrupt pending.
Bit 4
A 0 indicates that a match has been found after the last RESET or
REINITIALIZE STATUS BYTE command. A1 indicates no match was
found. See Table 11 to determine where the match occurred.
Bit 5
A 0 indicates that an end-of-block was reached after the last
RESET, LOAD, CONTINUE, or REINITIALIZE STATUS BYTE
command. A 1 indicates no end-of-block was reached. See Table 12 to
determine the contents of counters when the DMA stops.
Bit 6
Undefined.
Bit 7
Undefined.