Zilog Z08470 - Manual (Page 89)

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Figure 29. Z80 DMA Block Diagram
System
Data
Bus
(8-Bit)
System
Data
Bus
(16-Bit)
Control
Interrupt
and Bus
Priority
Logic
Pulse
Logic
Bus
Control
Logic
Control
and
Status
Registers
BYTE
Match
Logic
BYTE
Counter
Internal Bus MUX
Port A
Address
Port B
Address