Zilog Z08470 - Manual (Page 37)

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UM008101-0601 Counter/Timer Channels
automatic features in the interrupt control logic, one pre-programmed
interrupt vector suffices for all four channels.
Loading The Channel Control Register
To load a Channel Control Word, the CPU performs a normal I/O Write
sequence to the port address corresponding to the desired CTC channel. The
CTC input pins CS0 and CS1 are used to form a 2-bit binary address to select
one of four channels within the device. (See Table 2 on page 5.) In many
system architectures, these two input pins are connected to Address Bus lines
A0 and A1, respectively, so that the four channels in a CTC device occupy
contiguous I/O port addresses. A word written to a CTC channel is
interpreted as a channel control word, and loaded into the channel control
register (bit 0 is a logic 1). The other seven bits of this word select operating
modes and conditions as indicated in Table 2.
Table 5. Channel Control Register
7 6 5 4 3 2 1 0
Interrupt Mode Prescaler
Value* CLK/TRG
Section Time
Trigger* Time
Constant Reset Control or
Vector
R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Number
Field R/W Value Description
7 Interrupt R/W 1
0 Enable Interrupt
Disable Interrupt
6 Mode R/W 1
0 COUNTER Mode
TIMER Mode
5 Prescaler Value* R/W 1
0 256
16
*TIMER mode only