Zilog Z08470 - Manual (Page 75)

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UM008101-0601 Direct Memory Access
Address Generation
Two 26-bit addresses are generated by the DMA for every transfer oper-
ation: one address for the source port and another for the destination port.
The two addresses are multiplexed onto the address bus, according to
whether the DMA is reading the source or writing to the destination.
The two ports are arbitrarily named Port A and Port B. Both A and B can be
either source or destination, either memory or I/O, and have fixed or
variable addresses.
Table 8. Maximum Transfer and Search Speeds (Burst and Continuous
Modes)
Action
Z80
(2.4 MHz) Z80Z
(4.0 MHz)
DMA Simultaneous Transfer 1.25
MB/s 2.0
MB/s
DMA Search Only
DMA Simultaneous Transfer/Search
DMA Sequential Transfer 0.625
MB/s 1.0
MB/s
DMA Sequential Transfer/Search
CPU Block Transfer Instruction 0.125
MB/s 0.200
MB/s
Table 9. Reduction in Z80 CPU Throughput per Kbaud
(Byte Mode Transfers)
Action
Z80
(2.4 MHz) Z80Z
(4.0 MHz)
DMA Sequential Transfer 0.085% 0.041%
DMA Sequential Transfer/Search
CPU Interrupt Driven Transfer 0.340% 0.213%