Zilog Z08470 - Manual (Page 302)

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UM008101-0601 Serial Input/Output
282
Figure 116. Write Register 2
Write Register 3
WR3 ( Figure 117 ) contains receiver logic control bits and parameters.
(Table 20)
Receiver Enable (D0)
A 1 programmed into this bit allows receive operations to begin. Set this bit
only after all other receive parameters are set and the receiver is completely
initialized.
Table 20. Write Register 3 Logic Control
D7 D6 D5 D4
Receiver Bits/
Chars
Receiver Bits/Char
0
Auto Enables Enter Hunt Phase
D3 D2 D1 D0
Receiver CRC
Enable
Address Search
Mode
Sync Char Load
Inhibit
Receiver Enable
V0
V1
V2
V3
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt
V4
V5
V6
V7
Vector