Zilog Z08470 - Manual (Page 107)

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7UGT /CPWCN
UM008101-0601 Direct Memory Access
are allowed in which the higher priority peripheral suspends the execution
of the lower priority peripheral’s service routine.
Bus-requesting daisy-chains do not have this preemption or nesting
ability. Instead, any peripheral that is able to get the bus keeps it until task
completion.
Figure 37. Interrupt Daisy-Chain
Polling for Service Requests
When the CPU cannot detect interrupts directly, it polls an external gate as
shown in Figure 38.
Polling is accomplished in the following way:
•
Enable the DMA’s interrupt structure with a control byte
•
Poll a status bit to see when an interrupt request occurs
+5V
Z80
CPU
INT
IEI
INT
IEO
INT
Highest Priority
Interrupting Device
IEI IEO
To
Lower
Priority
Interrupting
Device
DMA
tristate enable line, normally at tristate,
for example, connected to a chip select decoder.
Pending
Polling
CPU
INT