Figure 8, Mode 2 interrupt operation, Table 7 – Zilog Z08470 User Manual
Page 41: Interrupt vector register, Figure 8)
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UM008101-0601
Counter/Timer Channels
Figure 8.
Mode 2 Interrupt Operation
Table 7. Interrupt Vector Register
7
6
5
4
3
2
1
0
Supplied by User
Channel Identifier
Word
R/W
R/W
R/W
Bit
Number
Field
R/W
Value
Description
7–3
Reserved
R/W
Supplied by User
2–1
Channel
Identifier
R/W
11
10
01
00
Channel 3
Channel 2
Channel 1
Channel 0
0
Word
R/W
1
0
Control
Interrupt Vector
Service Interrupt Routine
Starting Address
Low Order
High Order
Desired starting address pointed to by:
1 Reg
Contents
7 Bits from
Peripheral
0