Figure 115. write register 1, Table 36, Receive interrupt modes – Zilog Z08470 User Manual
Page 299

Z80 CPU Peripherals
User Manual
UM008101-0601
Serial Input/Output
279
Figure 115. Write Register 1
Wait/Ready Function Selection (D7-D5). The Wait and Ready functions are
selected by controlling D5, D6, and D7. Wait/Ready function is enabled by
setting Wait/Ready Enable (WR1, D7) to 1. The Ready function is selected
by setting D5 (Wait/Ready function) to 1. If this bit is 1, the WAIT/READY
output switches from High to Low when the Z80 SIO is ready to transfer
Table 17. Receive Interrupt Modes
D4
Receive
Interrupt Mode
1
D3
Receive
Interrupt Mode
0
Result
0
0
Receive Interrupts Disabled
0
1
Receive Interrupt On First Character Only
1
0
Interrupt On All Receive Characters
−
parity error is a Special Receive condition
1
1
Interrupt On All Receive Characters
−
parity error is not a Special Receive
condition
0
0
0
1
1
0
1
1
Rx INT Disable
Rx INT on First Character
INT on All Rx Characters (Parity Affects Vector)
INT on All Rx Characters (Parity Does Not Affect Vector)
EXE INT Enable
Tx INT Enable
Status Affects Vector
(CH.B Only)
Wait/Ready on R/T
Wait/Ready Function
Wait/Ready Enable
D7
D6
D5
D4
D3
D2
D1
D0
*Or on special condition
*