Zilog Z08470 - Manual (Page 171)

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UM008101-0601 Direct Memory Access
Figure 60. CPU-to-DMA Read Cycle Requirements
The DMA As Bus Master
Sequential Transfers
In sequential transfer and transfer/search operations, which both have the
same timing, data is latched onto the bus by the rising edge of the RD sig-
nal, with standard timing this is the falling edge of T3. Data is held on the
data bus across the boundary between read and write cycles, through the
end of the following write cycle. The DMA data bus drivers become active
when RD becomes inactive.
Figure 61 illustrates the timing for memory-to-I/O port transfers, and
Figure 62 illustrates I/O-to-memory transfers. Memory-to-memory and I/O
to-I/O transfer timings are simply permutations of these diagrams.
The default timing uses three clock cycles for memory transactions and
four clock cycles for I/O transactions, which include one automatically
inserted wait cycle between T2 and T3. If the CE/WAIT line is pro-
grammed to serve as a WAIT line during the DMA’s active state, it is sam-
pled on the falling edge of T2 for memory transactions and the falling edge
of TW for I/O transactions. If CE/WAIT is Low during this time, another T-
cycle is added, during which time the CE/WAIT line is again sampled. The
duration of transactions can thus be indefinitely extended.
CLK
CE
IORQ
WR
D7–D0