Zilog Z08470 - Manual (Page 120)

< %27 2GTKRJGTCNU
7UGT /CPWCN
UM008101-0601 Direct Memory Access
Interrupt Vector
Bit 4 of the interrupt control byte allows the interrupt vector to be entered.
In addition, when bit 5 of the interrupt control byte (Status Affects Vector)
is set to 1, bits 1 and 2 of the interrupt vector are modified to reflect the
cause of the interrupt (for example, the state of the Ready line or Status
latches) before the vector is placed on the data bus in response to the CPU’s
interrupt acknowledge.
The Status Affects Vector mode must not be used when both Auto Restart
and interrupt on end-of-block have been programmed. The interrupt vector
sent at the end of each block in this case cannot be modified to reflect the
end-of-block status.
Pulse Generation
Pulse generation is caused by (1) pointing to the interrupt control byte with
the base register byte, (2) setting bits 2 and 3 of the interrupt control byte,
and (3) entering an offset value in the pulse control byte. The pulse control
byte is compared with the lower byte of the byte counter and a pulse is
generated on the INT line whenever a match occurs, which is every 256-
byte transfers or searches after the initial offset number of bytes.