Zilog Z08470 - Manual (Page 109)

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UM008101-0601 Direct Memory Access
chapter. It is not possible for the DMA to program itself by directing
transfers of control bytes from memory to its own internal registers.
When DMA interrupt vectors are used in a Z80 environment, the Z80 CPU
should be programmed for Mode-2 maskable interrupts.
Table 13. DMA Status
DISABLED ENABLED
ACTIVE
Inactive (Stopped) Suspended Operating
Description DMA cannot request the bus (cannot pull
its BUSREQ input to CPU low). DMA can request the bus
and may have had the bus
immediately prior to this
state, but it is not
currently the bus master. DMA is bus
master but no
operations are
taking place. DMA is bus master
and is transferring and/
or searching in one of
three modes: Byte,
Burst, or Continuous
Can the CPU
write DMA
control bytes
or read DMA
status bytes? Yes Yes, but first write a
DISABLE DMA
command No No
External
actions that
cause the
state Power-down End-of-block in any
mode, except with Auto
Restart. Byte Match in
any mode. Byte or Burst
mode BAI line inactive.
Loss of power. RDY line
inactive in
Continuous
mode. RDY line active in
Burst mode, if DMA is
enabled. RETI
instruction fetched by
CPU, if DMA is
enabled and RDY line
is active.
DMA
commands
(WR6 control
bytes)
causing the
state Any command except the ENABLE DMA
command. (And the REINITIALIZE
STATUS BYTE command, if it is not
preceded by another command.) The
DISABLE DMA command is specifically
designed for this situation. ENABLE DMA if RDY
line is inactive and the
FORCE READY
command is not used. ENABLE
DMA, if RDY
line is inactive
in Continuous
mode. ENABLE DMA, if
RDY is active or the
FORCE is used and
the command is
outside an interrupt
service routine.