Zilog Z08470 - Manual (Page 289)

Z80 CPU Peripherals
User Manual
UM008101-0601 Serial Input/Output
269
WR4 Parity information, Sync Mode, SDLC
Mode, X1 Clock Mode
WR0 Pointer 5, Reset External/Status
Interrupts
WR5 SDLC-CRC, Data Terminal Ready
WR0 Pointer 3
WR3 Receive CRC Enable, enter Hunt Mode,
Auto Enables, Receive Character Length,
Address Search Mode Auto Enables enables the receiver to
accept data only after MB becomes
active. Address Search Mode Enables
SIO to match the message address
with the programmed address or the
global address.
WR0 Pointer 6
WR6 Secondary Address Field This address is compared to the
message address in an SDLC Poll
operation.
WR0 Pointer 7
WR7 SDLC Flag 0111 1110 This flag detects the start and end-of-
frame in an SDLC Operation. In this
Interrupt Mode, only the address field
(1 character only) is transferred to the
CPU. All subsequent fields (control,
information, and more.) are
transferred on a DMA basis. Status
Affects Vector in Channel B only.
WR0 Pointer 1, Reset External/Status
Interrupts
WR1 Status Affects Vector, External Interrupt
Enable, Receive Interrupt on first
character only.
WR0 Pointer 3, Enable Interrupt on next
Receive Character This flag provides simple loop-back
entry point for next transaction.
WR3 Receive Enable, Receive CRC Enable,
enter Hunt Mode, Auto Enables,
Receiver Character Length, Address
Search Mode WR3 reissued to enable receiver.
Table 10. SDLC Receive Mode (Continued)
Function Typical Program Steps Comments