Zilog Z08470 - Manual (Page 150)

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UM008101-0601 Direct Memory Access
Figure 49. Chip Enable Decoding with Z80 CPU
Use of WAIT Input
When the DMA is bus master, the CE/WAIT pin functions as an input from
memory or I/O logic that may extend read or write cycles by requesting
Waits states. An active BUSACK output from the CPU signals that the
Z80
CPU
M1
IORQ
CPU
M1
IORQ
DMA
M1 IORQ CE
DMA
M1 IORQ CE
CE7
CE1
A2
A3 A4
CE3
CE2
CE1
A5
A0
A7
A7
A0
A DMA responds to
I/O addresses 00H
through 77H
B PROM determines
DMA response
C DMA responds to
I/O addresses E0H
through E3H
DMA
M1 IORQ CE
Address Bus
A7
A7
A0
04
03
02
01
256X4
PROM
CPU
M1
IORQ 1 2 3 4 5 6 7 0
74LS138
S0 S1 S2
E
E
E
.
.
.
.