Zilog Z08470 - Manual (Page 135)

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UM008101-0601 Direct Memory Access
Figure 47. Read Register 0 through Read Register 6
Byte Counter (RR1, RR2)
This 16-bit counter is cleared to 0 by the LOAD, CONTINUE, and RESET
commands only. When the DMA begins transferring or searching, the byte
counter increments by one at the end of each read cycle and the byte counter
is compared with the programmed contents of the block length register,
determining end-of-block. The number of bytes read in a transfer always
equals the number of bytes written because the DMA completes any transfer
it starts, even when stopping on byte matches in transfer/search operations.
D7 D6 D5 D4 D3 D2 D1 D0
Status Byte X X
1 = DMA Operation has Occurred
0 = Ready Active
0 = Interrupt Pending
0 = Match Found
0 = End-of-Block
Byte Counter (Low Byte)
Read Register 1
Byte Counter (High Byte)
Read Register 2
Port A Address Counter (Low Byte)
Read Register 3
Port A Address Counter (High Byte)
Read Register 4
Port B Address Counter (Low Byte)
Read Register 5
Port B Address Counter (High Byte)
Read Register 6