Zilog Z08470 - Manual (Page 191)

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7UGT /CPWCN
UM008101-0601 Direct Memory Access
Figure 80. Write Register 4 Group
D7 D6 D5 D4 D3 D2 D1 D0
Base Register Byte
0
0
0
0
= Interrupt on End-of-Block
= Interrupt on Match and
= Interrupt on RDY
0 1 1
Port B Starting Address
Pulse Control Byte
Interrupt on RDY = 1
Status Affects Vector = 1 1 = Pulse Generated
Interrupt Vector
End-of-Block
0
0
0
0
Modified as
Shown only if
‘Status Affects Vector’
Vector is Automatically
Bit is Set
1 = Interrupted at End-of-Block
1 = Interrupted on Match
0 Interrupt Control Byte
(High Byte)
Port B Starting Address
(Low Byte)
0
1
0
1 0
0
1
1
Continuous =
Burst =
Do Not Program =
Byte =
= Interrupt on Match