Zilog Z08470 - Manual (Page 197)

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UM008101-0601 Parallel Input/Output
The 2-bit mode control register is loaded by the CPU to select the desired
operating mode (byte output, byte input, byte bidirectional bus, or bit
control mode). All data transfer between the peripheral device and the
CPU is achieved through the data input and data output registers. Data
may be written into the output register by the CPU or read back to the
CPU from the input register at any time. The handshake lines associated
with each port are used to control the data transfer between the PIO and
the peripheral device.
Figure 1. PIO Block Diagram
+5V GND Φ
CPU
Interface
8
6
Data Bus
PIO Control
Lines
Internal Bus
Interrupt Control Lines
Internal Control
Interrupt Control
Data or Control
Handshake
8
8
Data or Control
Handshake
Peripheral
Interface
Port
A
I/O
Port
B
I/O
3
Logic