Zilog Z08470 - Manual (Page 60)

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UM008101-0601 Direct Memory Access
For example, the Z80 DMA can be programmed either to stop, interrupt the
CPU, continue, or repeat a transfer when a target event such as an end-of-
block, byte match, or Ready-line condition is reached. Alternatively, its
buffered address counters can be reloaded during one byte-mode transfer so
that the next transfer can begin quickly at a new location. Also, entire read
and write cycle timings can be modified independently for each port to fit
the requirements of other CPUs, memory, or I/O devices that are faster or
slower than the standard Z80 Family timing.
This topic, as well as the others described earlier, are expanded in following
chapters. They are introduced here to give a generalized framework from
which to launch a more detailed discussion of the Z80 DMA.
(See also Figure 20 through Figure 23).
Figure 17. Modes of Operation
BYTE
(Single)
BURST
(Demand)
CONTINUOUS
(Block)
YES
NO
YES
NO
Release
Control
RDY
Active
?
Release
Control
Transfer
Byte
Request
Control
YES
NO
Transfer
Byte
Request
Control
Transfer
Byte
Request
Control
RDY
Active
?
RDY
Active
?