Zilog Z08470 - Manual (Page 160)

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UM008101-0601 Direct Memory Access
represent the fractional reductions in CPU throughput per Kbaud trans-
ferred.
The DMA has a shorter and more predictable latency period and decreases
system overhead by at least a factor of five in this conservative example.
A diagram of a typical Z80 system using a Z80 CPU, a Z80 CTC for asyn-
chronous baud rate generation, both channels of a Z80 SIO, and two Z80
DMAs (one for each serial channel) appears in Figure 55. The diagram
omits the system memory (ROM and RAM), bus buffers (as required), and
chip enable decoders, which are described above.
Z80
(2.5 MHz) Z80A
(4 MHz)
DMA sequential transfer 0.065% 0.041%
DMA sequential transfer/search
Interrupt-driven transfer 0.340% 0.213%