Zilog Z08470 - Manual (Page 188)

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UM008101-0601 Direct Memory Access
Figure 75. Interrupt Acknowledge
A7–A0
RD
WAIT
CLOCK
IN
INT
DATA
BUS
M1
IORQ
MREQ
PC
Last M Cycle
of Instruction
T
1
Last T State
M1
Refresh
T
2
T
W
T
3
T
W