Zilog Z08470 - Manual (Page 207)

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7UGT /CPWCN
UM008101-0601 Parallel Input/Output
Figure 6. 40-Pin DIP Pin Assignments
PROGRAMMING THE PIO
Reset
The Z80 PIO automatically enters a reset state when power is applied. The
reset state performs the following functions:
1. Both port mask registers are reset to inhibit all port data bits.
2. Port data bus lines are set to a high-impedance state and the Ready
handshake signals are inactive (Low). Mode 1 is automatically selected.
3. The vector address registers are not reset.
4. Both port interrupt enable flip-flops are reset.
5. Both port output registers are reset.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Z80
PIO
D
2
D
7
D
6
CE
C/D
B/A
PA
7
PA
6
PA
5
PA
4
GND
PA
3
PA
2
PA
1
PA
0
ASTB
BSTB
ARDY
D
0
D
1
D
3
D
4
D
5
M1
IORQ
RD
PB
7
PB
6
PB
5
PB
4
PB
3
PB
2
PB
1
PB
0
+5V
CLK
IEI
INT
IEO
BRDY