Zilog Z08470 - Manual (Page 22)

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UM008101-0601 Counter/Timer Channels
In Channel Control Register and Logic
The Channel Control register (8-bit) and Logic is written to by the CPU to
select the modes and parameters of the channel. Within the CTC device,
four such registers correspond to the four Counter/Timer channels. The
register to be written to is determined by the encoding of two channel select
input pins: CS0 and CS1, which are usually attached to A0 and A1 of the
CPU address bus. The channel values are described in Table 1.
In the control word, which is written to program each Channel Control
register, bit 0 is always set; the other seven bits are programmed to select
alternatives on the channel’s operating modes and parameters. These values
are described in Table 2. For a more complete discussion, see “CTC
Operating Modes” on page 16 and “CTC Programming” on page 18).
Figure 2. Channel Block Diagram
Table 1. Channel Values
CS0 CS1
Channel 0 0 0
Channel 1 0 1
Channel 2 1 0
Channel 3 1 1
ZC/TO
Prescaler CLK
CLK/TRG
Internal Bus
8-Bit
Down
Counter
Time
Constant
Register
Channel
Control
Logic