Zilog Z08470 - Manual (Page 103)

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7UGT /CPWCN
UM008101-0601 Direct Memory Access
– Prevents interrupts from lower priority devices in an interrupt
daisy-chain
– Prevents further bus requests by this DMA
If the Interrupt on RDY (interrupt before requesting bus) option is selected,
the IP latch is set when the Ready line becomes active, causing INT to go
Low.
The IP latch is reset whenever the IUS latch is se. If the interrupt causing
condition is not removed before IUS reset, IP becomes set again after IUS
reset, causing another interrupt. The US latch can be reset by the Z80
CPU’s Return from Interrupt (RETI) instruction or by control bytes written
to the DMA.
Figure 34. Interrupt Pending (IP) Latch
Figure 35. Interrupt Under Service (IUS) Latch
Reinitialize Status Byte
Reset and Disable Interrupts
*NOTE: Interrupt conditions can include end-of-block,
byte match, or active RDY line, depending on programming.
M1 Inactive
Interrupt Condition
Enable Interrupts
Disable Interrupts
S
R
Q
S
R
IP
O
Interrupt Pending
(To IUS Latch Set)
S
R
IUS
O Disable DMA
Reset and Disable Interrupts
RETI
IEI
Interrupt Acknowledge
(M1 and IORQ)
Interrupt Pending
(from IP Latch)