Figure 32. z80 interrupt sequence, Interrupt vectors – Zilog Z08470 User Manual
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Direct Memory Access
Figure 32.
Z80 Interrupt Sequence
Interrupt Vectors
The Z80 CPU interrupt acknowledge cycle causes the DMA to put its 8-bit
interrupt vector on the data bus (Figure 33a). This vector is read by the
DMA
CPU
End-of-Block
or Byte Match
DMA Releases
Bus and
Interrupts CPU
CPU Acknowledges
Interrupt
DMA Passes
Interrupt Vector
to CPU
CPU Executes
Interrupt Service
Routine
DMA Requests
Bus Again
*
*Bus Master
*
*
*
BUSREQ
BAI
BUSREQ
BUSACK
INT
INT
M1
IORQ
M1
IORQ
MEMORY
BUSREQ
BAI
BUSREQ
BUSACK