Zilog Z08470 - Manual (Page 290)

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UM008101-0601 Serial Input/Output
270
Idle Mode Execute Halt Instruction or some other
program SDLC Receive Mode is fully
initialized and SIO is waiting for the
opening flag followed by a matching
address field to interrupt the CPU.
Data Transfer and
Status
Monitoring When Interrupt On First Character
occurs, the CPU
performs the following: During the Hunt Phase, the SIO
interrupts when the programmed
address matches the message address.
The CPU establishes the DMA Mode
and all subsequent data characters are
transferred by the DMA controller to
memory.
• Transfers Data Byte (address byte) to
CPU
• Detects And Sets appropriate Flag for
Extended Address Field
• Updates pointers and parameters
• Enables DMA Controller
• Enables Wait/Ready function in SIO
• Returns from Interrupt
When the Ready Output becomes active,
the DMA Controller performs the
following:
During the DMA operation, the SIO
monitors the DCD Input and the Abort
sequence in the data stream to
interrupt the CPU with external status
error. The special receive condition
interrupt is caused by the Receive
Overrun Error.
• Transfers the Data Byte to memory
• Updates the pointers
Table 10. SDLC Receive Mode (Continued)
Function Typical Program Steps Comments